Cyclone 10 power-up latches up

Hi,

once again thank you for your time and interest in my problem.

The conf_done line also remains low. In fact I think all the pins of the chip (except for the power pins of course) appear to be low and sinking current which is why I thought it might be some kind of problem with the chip latching up during power-up.

I have added an image that shows the rise of the 3 power rails at power up:

Orange is 3V3

Blue is 2V5

Purple is 1V2

Do they look ok to you?

I think I read something about "if an IO pin has a high signal on it, before power is applied to the chip this may cause a latch-up". Do you know if this is correct?

Many of the IO pins of the FPGA are connected to other devices in the design and I have not checked all pins to ensure that the above does not happen. The 3 power lines for the FPGA are themselves derived from a 5V PSU and it is possible that other devices which power directly from this 5V (although with 3V3 IO) may "come up" faster than the FPGA's own power lines.

Should I be concerned for this?

Kind regards

PhilipJ