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mindchasers's avatar
mindchasers
Icon for New Contributor rankNew Contributor
4 years ago

Cyclone 10 GX ATX PLL questions

Hello,

Two questions regarding Cyclone 10 GX ATX PLLs:

1) When configuring the ATX PLL in Quartus Prime Pro 21.4 IP Parameter GUI, there is a field for VCO bandwidth. I can set this as low, medium, and high. Where can I find guidelines on the best setting to use for my particular configuration?

2) Section 3.1.1 of the "Transceiver PHY User Guide" version 20.1, specifies that "ATX PLLs' VCO frequency offset must be 100 MHz apart". What is "frequency offset" in this context? Is this the same thing as "PLL output frequency"? Will Quartus provide a warning or error if I violate this rule?

Thank you.

3 Replies

  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hello,

    1. ATX pll VCO bandwidth allows you to choose the optimized VCO frequency ;

    • Low—PLL with a low bandwidth has better jitter rejection but a slower lock time.
    • High—PLL with a high bandwidth has a faster lock time but tracks more jitter.
    • Medium—A medium bandwidth offers a balance between lock time and jitter rejection.

    2. This only requires when you recalibrate the transceivers , refer Chapter 7.4.1.

    regards,

    Farabi

    • mindchasers's avatar
      mindchasers
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi Farabi,

      Sorry for the delay in responding to your reply.

      Regarding bandwidth settings, thank you for that explanation, and I accept your answer.

      Regarding my questions on Section 3.1.1, I don't think you answered them; however, you did provide the context for when the rules must be followed. I'll just restate the questions:

      Section 3.1.1 of the "Transceiver PHY User Guide" version 20.1, specifies that "ATX PLLs' VCO frequency offset must be 100 MHz apart". What is "frequency offset" in this context? Is this the same thing as "PLL output frequency"? Will Quartus provide a warning or error if I violate this rule?

      We do have designs that instantiate multiple PLLs, and we intend to perform recalibration, so I want to make sure I fully understand the rules on separation.

      Thank you.

  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hello,

    We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

    best regards,

    Farabi