New Contributor
Regular ContributorHello,
1. ATX pll VCO bandwidth allows you to choose the optimized VCO frequency ;
• Low—PLL with a low bandwidth has better jitter rejection but a slower lock time.
• High—PLL with a high bandwidth has a faster lock time but tracks more jitter.
• Medium—A medium bandwidth offers a balance between lock time and jitter rejection.
2. This only requires when you recalibrate the transceivers , refer Chapter 7.4.1.
regards,
Farabi
New ContributorHi Farabi,
Sorry for the delay in responding to your reply.
Regarding bandwidth settings, thank you for that explanation, and I accept your answer.
Regarding my questions on Section 3.1.1, I don't think you answered them; however, you did provide the context for when the rules must be followed. I'll just restate the questions:
Section 3.1.1 of the "Transceiver PHY User Guide" version 20.1, specifies that "ATX PLLs' VCO frequency offset must be 100 MHz apart". What is "frequency offset" in this context? Is this the same thing as "PLL output frequency"? Will Quartus provide a warning or error if I violate this rule?
We do have designs that instantiate multiple PLLs, and we intend to perform recalibration, so I want to make sure I fully understand the rules on separation.
Thank you.
