sidsinha89New Contributor4 years agoCyclone 10 GX (10CX085F672) Device Clock input Hello All, I am starting to work with Intel FPGAs. I am currently preparing specifications for the new FPGA project. A part of it is to define pin assignment for the module. In my design, I wish ...Show More
Ash_R_IntelRegular Contributor4 years agoHI,Yes, you can use the n pin independently as a normal IO.Regards.
Recent DiscussionsAvalon-ST configuration with Agilex 3 failsCyclone IV E – PLL Power Track Width Recommendation ClarificationOperating temperature for 10M08DCF256A7GSystem PLL of Agliex5 PCIE example design cannot be locked after configurationDownload links not working