Cyc V-SOC Dev-Board LVDS with different clocks via HSMC-Connector

Hello,

As I do not know whether my problem only applies to the Cyclone V SOC or not, I decided to post my problem here:

My setting consists of the Cyclone V SOC dev kit I mentioned already in the title (with hardware SERDES, if that matters) and a Cyclone IV board (with SERDES in logic cells).

My goal is to input parallel data with 80MHz and a width of 48bit into the Cyclone IV, send it via SERDES (6 channels, deserialization factor of 8) to the Cyclone V and reconstruct the 48bit-vector (and the other way round).

Therefore I have: 1 SERDES-TX and 1 SERDES-RX per side (I used the altlvds megafunctions), each SERDES-TX clocks (or at least: should clock) the SERDES-RX of the opposite side. The serial data (and the resulting two clocks) shall be transmitted via LVDS over the HSMC connector.

There, I am not absolutely sure which bank to use, but if I am right, the need of 6 channels and LVDS limits me to HSMA_TX_D and HSMA_RX_D?

I hope this explains my configuration which leads to following error:

As Quartus tries to create a fractional PLL for both, tx and rx, and wants to place them as near as possible to the input (respectively output) pin, it cannot complete this task and gives the following error message:

Error (175020): Illegal constraint of fractional PLL to the region (0, 73) to (0, 81): no valid locations in region
    Info (175028): The fractional PLL name: serdes_rx:serdes_rx1|altlvds_rx:ALTLVDS_RX_component|serdes_rx_lvds_rx:auto_generated|pll_sclk~FRACTIONAL_PLL
    Info (175013): The fractional PLL is constrained to the region (0, 73) to (0, 80) due to related logic
        Info (175014): Region must be within (0, 73) to (0, 80) due to the signal(s) routed from the fractional PLL to PLL output counter serdes_rx:serdes_rx1|altlvds_rx:ALTLVDS_RX_component|serdes_rx_lvds_rx:auto_generated|pll_fclk~PLL_OUTPUT_COUNTER
        Info (175014): Region must be within (0, 73) to (0, 81) due to the signal(s) routed from the PLL output counter to PLL LVDS output serdes_rx:serdes_rx1|altlvds_rx:ALTLVDS_RX_component|serdes_rx_lvds_rx:auto_generated|pll_ena~PLL_LVDS_OUTPUT
        Info (175014): Region must be within (0, 74) to (0, 75) due to the signal(s) routed from the PLL LVDS output to pin HSMA_RX_D
        Info (175015): The I/O pad is constrained to the location PIN_H14 due to: User Location Constraints (PIN_H14)
    Error (11238): Node is not compatible with other nodes placed at the same location either because there are too few available fractional PLL locations, or the nodes have different inputs, parameters, or both.
        Error (11239): Could not merge with previously placed fractional PLLs at location FRACTIONALPLL_X0_Y74_N0
            Info (11237): Already placed at this location: fractional PLL serdes_tx:serdes_tx1|altlvds_tx:ALTLVDS_TX_component|serdes_tx_lvds_tx:auto_generated|pll_fclk~FRACTIONAL_PLL
                Info (175013): The fractional PLL is constrained to the region (0, 31) to (0, 81) due to related logic
                    Info (175014): Region must be within (0, 31) to (0, 81) due to the signal(s) routed from pin clk_in to the fractional PLL
                    Info (175013): The pin is constrained to the region (7, 81) to (32, 81) due to related logic
                        Info (175034): Assignment 1: Region must be in (7, 81) to (40, 81) due to the constraint on I/O pad clk_in, which is a part of pin clk_in
                            Info (175015): The I/O pad is constrained to the location PIN_K14 due to: User Location Constraints (PIN_K14)
                        Info (175034): Assignment 2: Region must be in (7, 81) to (32, 81) due to the signal(s) routed from the pin to fractional PLL serdes_tx:serdes_tx1|altlvds_tx:ALTLVDS_TX_component|serdes_tx_lvds_tx:auto_generated|pll_fclk~FRACTIONAL_PLL
                            Info (175013): The fractional PLL is constrained to the region (0, 73) to (0, 80) due to related logic
                                Info (175034): Assignment 2: Region must be in (0, 73) to (0, 80) due to the signal(s) routed from the fractional PLL to PLL output counter serdes_tx:serdes_tx1|altlvds_tx:ALTLVDS_TX_component|serdes_tx_lvds_tx:auto_generated|pll_fclk~PLL_OUTPUT_COUNTER
                                    Info (175013): The PLL output counter is constrained to the region (0, 73) to (0, 81) due to related logic
Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.

What can I do to solve this? Is the idea to use the outclock of each tx block to feed the inclock of the corresponding rx block not the way things should be done? Replacing clk_in by a altclkctrl megafunction did not solve the problem either.

Any help is appreciated, thanks

herrhannes