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Altera_Forum
Honored Contributor
Honored ContributorCyc V-SOC Dev-Board LVDS with different clocks via HSMC-Connector
Hello, As I do not know whether my problem only applies to the Cyclone V SOC or not, I decided to post my problem here: My setting consists of the Cyclone V SOC dev kit I mentioned already...
Altera_ForumHonored Contributor
Honored ContributorDoes nobody know an answer or did I forget to mention something important?
Using an external PLL and constraining it manually to another location does also not solve the problem as these assignments are ignored by the fitter.
