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Altera_Forum's avatar
Altera_Forum
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12 years ago

Cyc V-SOC Dev-Board LVDS with different clocks via HSMC-Connector

Hello, As I do not know whether my problem only applies to the Cyclone V SOC or not, I decided to post my problem here: My setting consists of the Cyclone V SOC dev kit I mentioned already...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Maybe this page will help for you

http://www.altera.co.uk/support/kdb/solutions/rd03312013_521.html

I had the same problem, and the above page pointed me in the right direction. The QSF fix wasn't applicable for me, what I did was

  1. Go into the MegaWizard

  2. Edit the SERDES

  3. Go to Transmitter settings

  4. Enable "Use 'tx_coreclock' output port

  5. Change from "Dual Regional" to "Auto"

  6. Disable "Use 'tx_coreclock' output port

  7. Finish

Even though the box isn't highlighted, if you have it set to Dual Regional, it will fail to build.