custom peripheral memory-mapping issue

Problem solved, it was my fault, I didn't understand well how avalon bus addressing works :)

Since I've read many questions about register addressing in custom peripheral, but no one had been resolved, i will explain what i learned, in a simplified way:

when you define an address width for your logic, you are choosing how much registers you give to your peripheral;

for example, a width of 3 bits will lead to a maximum of 8 registers: 000,001,010,011 etc.

in the vhdl code of the hw, you decide what to do with every address (i.e. adding a case statement, case address is "000" => do something...etc.)

Since Nios address bus is 32 bit wide, avalon bus transforms this addresses into a 32-bit value in this way:

as first thing, a range of 32-bit addresses is assigned to your hw starting from the base address, every register is 4 byte wide; for example, with 3 bits address we will have a range given by base address, base+4 bytes, base+8 bytes...etc (up to 8 values in total). Every read operation accesses 4 bytes, so if you want to access the branch of the case statement related to address 001, you must type

IORD(base,4) that leads to an address of BASE_ADDR+4 bytes, and to access address 002 you must type IORD(base,8)...

writing IORD(base,0), IORD(base,1) , IORD(base,2) will have the same result of calling IORD(base,4), so to access different addresses and so different registers you must jump by multiples of 4 bytes (1 word in nios terminology).

Hope it was exausting :)