custom instructions implementation

Stefaan,

thank you for your reply. I haven't been at home over the weekend so that I wasn't able to write here.

My vhdl code isn't that complex to explain the ide's behaviour.

I'll show you:

--- Quote Start ---

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

library WORK;

entity mac is

Port ( A : in STD_LOGIC_VECTOR(15 downto 0);

B : in STD_LOGIC_VECTOR(15 downto 0);

C : in STD_LOGIC_VECTOR(31 downto 0);

Q : out STD_LOGIC_VECTOR(31 downto 0);

clk : in STD_LOGIC);

end mac;

architecture Behavioral of mac is

signal Qs : STD_LOGIC_VECTOR(31 downto 0);

begin

MAC : Process (CLK)

Begin

If CLK'event and CLK = '1' Then

Qs <= A*B;

End If;

End Process;

Q <= Qs + C;

end Behavioral;

--- Quote End ---

I guess I'll just try around a little. Maybe I'm lucky to find sth.

Thanks anyway again for the help.

Cheers,

Dash