Crossing clock domains?

OK. It's a 6809E processor. I know that, for instance, on the falling edge of the 'Q' clock, the Address bus has been set up for around 500ns and the Data bus has been set up for around 200ns. The hold time is going to be around 200-300ns.

So, if I want the FPGA to read the address/data bus, it looks like I could just clock them into registers on the falling edge of the synchronised Q clock. The address/data bus (and R/W etc) should be very stable by that moment, and not going to change for a while, so they shouldn't need more synchronisation.

If the CPU was going at a similar speed to the FPGA clock, then I can see that I may need more synchronisation, but because the speeds are so vastly different, I'm not sure it's needed. Also if I was trying to squeeze every ns out of it by running close to the timing limits of the 6809, but I'm not.

(It's not a timing problem to synchronise them, just using lots of registers unnecessarily AFAICS).