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Honored ContributorCROSS CLOCK vhdl
Hello Everybody, In my application I receive images from a camera that uses CAMERA LINK protocol (100 fps). The camera generates its own 40 MHz pixel clock. All the data's from the camera ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I frequently pass video across clock domains using dual-clock fifos. Simply use the empty signal on the read side of the FIFO as a datavalid or clock enable. All other signals should be passed as data through the FIFO. Jake --- Quote End --- Thats exactly what I do - works great. I see you mention you are doing billinear interpolation.. why do you need a 160 MHz clock? I get the feeling you are buffering up a line and then doing 4 reads to get your 4 pixel values. If you're only doing billinear interpolation (and nothing else) you can run it at 40MHz and just cope with a 1 line latency (which you'll get at 160MHz anyway). The pixels you need come from a line delay memory and a few registers, all clocked at input pixel frequency. Not knowing the full spec of the system, I cant really comment. But I assume you have a billinear interpolate as part of a Warp function?
