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Altera_Forum's avatar
Altera_Forum
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16 years ago

Creating delay using logic?

Hello again,

My latest challenge involves generating an SPI clock from an incoming stream of SPI data.

I've been successful in getting the MAX II to produce the SPI clock, however the data and clock are not aligned correctly by 1.5-3 clock cycles of the CPLD.

I was wondering what are my options in introducing delay without modifying the PIN delay as the design I'm working on should be back-compatible with other parts of the block design in quartus.

I've tried putting in shift registers with width of 1,2,3.

The results are:

Width of 1 produces a delay of one clock.

Width of 2 produces the same amount of delay as width of 1.

Width of 3 produces a delay of 3 clock cycles.

I don't understand why 2 doesn't do anything.

Thanks.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    generating an SPI clock from an incoming stream of SPI data

    --- Quote End ---

    It's neither clear, what you exactly want to achieve, nor what you are actually doing. The above description sounds like CDR (clock-data recovery), but it won't work with SPI in general, because SPI has no guaranteed clock edges.

    The problem would be clearer, if you showed some waveforms and your basic circuit, I think.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Nope, not to worry. I fixed it by delaying my clock generation with a shift register.