Create IRQ pin

Verilog:

wire signal_cpu2_to_cpu1;
wire signal_cpu1_to_cpu2;
Nios_system inst1(
   .clk(your_clock),
    .reset_n(your_reset),
    ....
    .in_port_to_the_cpu1_pio_in(signal_cpu2_to_cpu1),
    .in_port_to_the_cpu2_pio_in(signal_cpu1_to_cpu2),
    .out_port_from_the_cpu1_pio_out(signal_cpu1_to_cpu2),	
    .out_port_from_the_cpu2_pio_out(signal_cpu2_to_cpu1),	
    ....  );

SIGNAL signal_cpu1_to_cpu2 : STD_LOGIC;
SIGNAL signal_cpu2_to_cpu1 : STD_LOGIC;
COMPONENT Nios_system
    PORT (
        clk : IN std_logic;
        reset_n : IN std_logic;
        ....
       in_port_to_the_cpu1_pio_in : IN std_logic;
       in_port_to_the_cpu2_pio_in : IN std_logic;
       out_port_from_the_cpu1_pio_out : OUT std_logic;
       out_port_from_the_cpu2_pio_out : OUT std_logic;
    ....  );
END COMPONENT;
inst1 : Nios_system
PORT MAP  (
        clk >= your_clk,
        reset_n >= your_reset,
        ....
       in_port_to_the_cpu1_pio_in >= signal_cpu2_to_cpu1;
       in_port_to_the_cpu2_pio_in >= signal_cpu1_to_cpu2;
       out_port_from_the_cpu1_pio_out  >= signal_cpu1_to_cpu2;
       out_port_from_the_cpu2_pio_out  >= signal_cpu2_to_cpu1;
);