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Altera_Forum's avatar
Altera_Forum
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14 years ago

create_generated_clock

Hi,

Altera supports "create_generated_clock" constraints. I have few questions.

1. Does Altera supports gated clock conversion (like Synplify Pro)

2. If supports, what is the use of 'create_generated_clock' constrain.

Because after GCC, all flops will be connected to the master clock.

Please help me to understand.

Regards,

freak

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Quartus has an option to convert gated clocks to clock enables.

    create_generated_clock constrains are used when

    a) you use logic to divide a clock's frequency

    b) you use a PLL do derive a clock (although the derive_pll_clocks command does it automatically for you)

    c) you need to constrain a source synchronous interface (ie, you need to create a derived clock at the pin)

    d) ... probably a bunch of other situations
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    rbugalho: i remember playing with this feature in Quartus, and it didn't work how i wanted it to. have you? then again i haven't used Synplify

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    No, I never used it. I just prefer to always use clock enable style.

    ASIC tools seem more consistent at converting clock enables to clock gating than otherwise arround too.

    I have some faint recollection of someone managing to get it to work, but you need your clock gates to meet a supported template.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Well, I just tried it and it worked.

    - Using Timequest: http://quartushelp.altera.com/current/mergedprojects/logicops/logicops/def_synth_gated_clock_conversion.htm

    - Following Altera's clock gating guidelines: http://quartushelp.altera.com/9.1/mergedprojects/verify/da/comp_file_rules_clock.htm

    The code:

    -- Verilog

    module p1 (clk, enable, rx, tx);

    parameter MY_WIDTH = 2;

    input wire clk;

    input wire enable;

    input wire [MY_WIDTH-1:0] rx;

    output wire [MY_WIDTH-1:0] tx;

    wire clk2;

    clockGate cg(enable, clk, clk2);

    reg [MY_WIDTH-1:0] r;

    always @ (posedge clk2) begin

    r <= rx;

    end

    assign tx = r;

    endmodule

    module clockGate(

    input wire enable,

    input wire clkIn,

    output wire clkOut

    );

    reg q;

    always @ (negedge clkIn) begin

    q <= enable;

    end

    assign clkOut = q & clkIn;

    endmodule

    -- SDC

    create_clock -name clk -period 10 [get_ports clk]