create_generated_clock

Well, I just tried it and it worked.

- Using Timequest: http://quartushelp.altera.com/current/mergedprojects/logicops/logicops/def_synth_gated_clock_conversion.htm

- Following Altera's clock gating guidelines: http://quartushelp.altera.com/9.1/mergedprojects/verify/da/comp_file_rules_clock.htm

The code:

-- Verilog

module p1 (clk, enable, rx, tx);

parameter MY_WIDTH = 2;

input wire clk;

input wire enable;

input wire [MY_WIDTH-1:0] rx;

output wire [MY_WIDTH-1:0] tx;

wire clk2;

clockGate cg(enable, clk, clk2);

reg [MY_WIDTH-1:0] r;

always @ (posedge clk2) begin

r <= rx;

end

assign tx = r;

endmodule

module clockGate(

input wire enable,

input wire clkIn,

output wire clkOut

);

reg q;

always @ (negedge clkIn) begin

q <= enable;

end

assign clkOut = q & clkIn;

endmodule

-- SDC

create_clock -name clk -period 10 [get_ports clk]