Create delay between internal logics

normaly you should have a fully syncronize design where all logic registers are based upon a clock and the combinatorical delay betwee nregisters does not matters, the synthesis and timing analyzer will show how high the clock rate could be

designing a delay in a full synchron design is normaly done with pipelining a register, but you will delay N clocks the signal.

asyncron delay is due to different combinatorical legth between register output and input. but trusting in such delays can be very risky as the delay time depends upon the device and temperature and other criteria so can't say how the delay will be. for example if the device is cooled down, it gets faster so the setup time is getting critical.

specifying a delay for example in verilog with a# is for simulation purpose only and has no effect to the real design in the target