CPLD selection suggestion

I assume devices A & B are not FPGAs whose logic you have control over? Ordinarily you would not design an interface, operating at that speed, to clock out on one edge and in on the other.

Assuming you simply want to clock data into and out of the CPLD at that speed then you have a pretty wide choice to chose from. The MAX V family will do that - you may need something faster than the slowest (cheapest) speed grade.

However, you are transferring the problem inside the CPLD. You now effectively have two clock domains inside your CPLD, across which you need to transfer your data. You will need to implement some form of FIFO to carry the data across between clock domains.

Regards,

Alex