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Altera_Forum's avatar
Altera_Forum
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17 years ago

coupla n00b Q's on libraries

Hi we just started using Quartus on my course and we've come up stuck trying to create a library

the notes we have been following from Penn Uni

give the code: 

-- Package declaration
library ieee;
use ieee.std_logic_1164.all;
package basic_func is
     -- AND2 declaration
     component AND2
           generic (DELAY: time :=5ns);
           port (in1, in2: in std_logic; out1: out std_logic);
     end component;
     -- OR2 declaration
component OR2
           generic (DELAY: time :=5ns);
           port (in1, in2: in std_logic; out1: out std_logic);
     end component;
end package basic_func;
 
-- Package body declarations
library ieee;
use ieee.std_logic_1164.all;
package body basic_func is
     -- 2 input AND gate
     entity AND2 is
           generic (DELAY: time);
           port (in1, in2: in std_logic; out1: out std_logic);
     end AND2;
     architecture model_conc of AND2 is
           begin
                out1 <= in1 and in2 after DELAY;
     end model_conc;
-- 2 input OR gate
entity OR2 is
           generic (DELAY: time);
           port (in1, in2: in std_logic; out1: out std_logic);
     end OR2;
     architecture model_conc2 of AND2 is
           begin
                out1 <= in1 or in2 after DELAY;
     end model_conc2;
end package body basic_func;

but dont give much more on saving the file etc, I assume this has to be done in a certain way, as opposed to a simple vhd file, as when we try to call this from the actual program 

library  ieee, my_func;
use  ieee.std_logic_1164.all, my_func.basic_func.all;
--...rest of prog

we're getting loads of errors like this however

we are fairly clueless on this point, do we have to create the library differently? in a package?

any help much appreciated!! :)

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Without specifying an alternative library, all package code goes to default library work and

    could be made available like this 

    LIBRARY work;
USE work.<packagename>.all;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    How to add to work library?

    I save the file with package code as a VHDL file in my local project folder (not the general Altera base folder, as we work from network drives)

    then what?

    has this been automatically added to work lib?

    where is work lib?

    + more random dumb q's.....

    bear in mind am total noob to creating packages/libraries, so if you could elaborate would be great

    thanks!
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hello,

    it's as you expect: All your project files are compiled to the library work. From a users view, it's only a name space for packages. You can use it e. g. for project wide function, type and constant definitions.

    Regards,

    Frank
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hi

    so have 

    library  ieee, work;
use  ieee.std_logic_1164.all, work.basic_func.all;
    at the start of my code now, with basic_func.vhdl stored in my project directory

    but still have same errors. the main one being

    Error: VHDL Use Clause error at buzzer.vhd(4): design library "work" does not contain primary unit "basic_func"

    then

    Error: Ignored construct buzzer at buzzer.vhd(6) because of previous errors -thus-

    Error: VHDL error at buzzer.vhd(11): entity "buzzer" is used but not declared

    and strangely

    Error: VHDL error at buzzer.vhd(14): object "std_logic" is used but not declared

    as if even the ieee.std_logic_1164 package is not being used????

    once again any help is much appreciated and much thanks for the help so far :)
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Correct syntax is like this: 

    library ieee;
use  ieee.std_logic_1164.all;
library work;
use work.basic_func.all;
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi thanks for persevering with me, I have altered as last post, but still have the same errors..

    my buzzer.vhd code is this: 

    -- Example of a car door, seatbelt, ignition buzzer.
-- Definition of buzzer.
library ieee;
use  ieee.std_logic_1164.all;
library work;
use work.basic_func.all;
entity buzzer is
	 port (DOOR, IGNITION, SBELT: in std_logic;
           WARNING: out std_logic);
end buzzer;
architecture structural of buzzer is
           -- Declarations of architectural components.
component AND21
	 port (in1, in2: in std_logic;
           out1: out std_logic);
end component;
component OR21
	 port (in1, in2: in std_logic;
           out1: out std_logic);
end component;
component NOT11
	 port (in1: in std_logic;
           out1: out std_logic);
end component;
	-- Declaration of signals used to interconnect gates
signal DOOR_NOT, SBELT_NOT, B1, B2: std_logic;
begin
-- Map architecture of buzzer i.e. connections between components.
-- Component instantiations statements
	 U0: NOT11 port map (DOOR, DOOR_NOT);
	 U1: NOT11 port map (SBELT, SBELT_NOT);
	 U2: AND21 port map (IGNITION, DOOR_NOT, B1);
	 U3: AND21 port map (IGNITION, SBELT_NOT, B2);
	 U4: OR21  port map (B1, B2, WARNING);
end structural;

    with my basic_func.vhd file (in the same directory) being: 

    -- Package declaration
library ieee;
use ieee.std_logic_1164.all;
package basic_func is
-- AND2 declaration
component AND21
           port (in1, in2: in std_logic; out1: out std_logic);
     end component;
-- OR2 declaration
component OR21
           port (in1, in2: in std_logic; out1: out std_logic);
     end component;
--NOT1 declaration
component NOT11
			port (in1: in std_logic; out1: out std_logic);
     end component;
end package basic_func;
 
-- Package body declarations
library ieee;
use ieee.std_logic_1164.all;
package body basic_func is
-- 2 input AND gate
entity AND21 is
           port (in1, in2: in std_logic; out1: out std_logic);
     end AND21;
     architecture model_conc of AND21 is
           begin
                out1 <= in1 and in2;
     end model_conc;
-- 2 input OR gate
entity OR21 is
           port (in1, in2: in std_logic; out1: out std_logic);
     end OR21;
     architecture model_conc2 of AND21 is
           begin
                out1 <= in1 or in2;
     end model_conc2;
-- 1 input NOT gate
entity NOT11 is
		port (in1: in std_logic; out1: out std_logic);
     end NOT11;
	architecture model_conc3 of NOT11 is
		  begin
			  out1 <= not in1;
	end model_conc3;
end package body basic_func;

    compile messages are: 

    Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
	Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition
	Info: Processing started: Thu Mar 06 11:25:31 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off buzzer -c buzzer
Error: VHDL Use Clause error at buzzer.vhd(7): design library "work" does not contain primary unit "basic_func"
Error: Ignored construct buzzer at buzzer.vhd(9) because of previous errors
Error: VHDL error at buzzer.vhd(14): entity "buzzer" is used but not declared
Error: VHDL error at buzzer.vhd(17): object "std_logic" is used but not declared
Error: VHDL error at buzzer.vhd(18): object "std_logic" is used but not declared
Error: VHDL error at buzzer.vhd(22): object "std_logic" is used but not declared
Error: VHDL error at buzzer.vhd(23): object "std_logic" is used but not declared
Error: VHDL error at buzzer.vhd(27): object "std_logic" is used but not declared
Error: VHDL error at buzzer.vhd(28): object "std_logic" is used but not declared
Error: VHDL error at buzzer.vhd(31): object "std_logic" is used but not declared
Error: VHDL error at buzzer.vhd(36): object "DOOR" is used but not declared
Error: VHDL error at buzzer.vhd(36): object "DOOR_NOT" is used but not declared
Error: VHDL error at buzzer.vhd(36): cannot associate formal port "out1" of mode "out" with an expression
Error: VHDL error at buzzer.vhd(37): object "SBELT" is used but not declared
Error: VHDL error at buzzer.vhd(37): object "SBELT_NOT" is used but not declared
Error: VHDL error at buzzer.vhd(37): cannot associate formal port "out1" of mode "out" with an expression
Error: VHDL error at buzzer.vhd(38): object "IGNITION" is used but not declared
Error: VHDL error at buzzer.vhd(38): object "DOOR_NOT" is used but not declared
Error: VHDL error at buzzer.vhd(38): object "B1" is used but not declared
Info: Found 0 design units, including 0 entities, in source file buzzer.vhd
Error: Quartus II Analysis & Synthesis was unsuccessful. 19 errors, 0 warnings
	Error: Processing ended: Thu Mar 06 11:25:32 2008
	Error: Elapsed time: 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 19 errors, 0 warnings

    I'm thinking maybe that I don't have the package code set out right, but can't figure out what it is...
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    When compiling in quartus, I believe the order of the list of files to compile does matter. Make sure your package file is at the top of the list. This could cause your first error message.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    hi

    thanks for that has solved the most alarming errors alright but still have a slew of errors.

    may be something fundamental as we are working from someone else's notes and they are not for Quartus (Xilinx Foundation synthesis program.), just VHDL!

    errors now are as: 

    Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
	Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition
	Info: Processing started: Mon Mar 10 16:55:35 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off buzzer_structural -c buzzer_structural
Error: VHDL syntax error at basic_func.vhd(26) near text "entity";  expecting "end", or a declaration statement, 
Error: VHDL syntax error at basic_func.vhd(29): name used in construct must match previously specified name "basic_func"
Error: Ignored construct basic_func at basic_func.vhd(24) because of previous errors
Error: VHDL error at basic_func.vhd(31): entity "AND2" is used but not declared
Error: VHDL error at basic_func.vhd(33): object "out1" is used but not declared
Error: VHDL error at basic_func.vhd(39): object "std_logic" is used but not declared
Error: Ignored construct OR2 at basic_func.vhd(37) because of previous errors
Error: VHDL error at basic_func.vhd(42): entity "AND2" is used but not declared
Error: VHDL error at basic_func.vhd(44): object "out1" is used but not declared
Error: VHDL syntax error at basic_func.vhd(46) near text "end";  expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"
Error: VHDL syntax error at basic_func.vhd(46) near text ";";  expecting "is"
Info: Found 0 design units, including 0 entities, in source file basic_func.vhd
Error: Quartus II Analysis & Synthesis was unsuccessful. 11 errors, 0 warnings
	Error: Processing ended: Mon Mar 10 16:55:36 2008
	Error: Elapsed time: 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 11 errors, 0 warnings

    sorry for asking on errors that seem to poin to something silly but have tried several combinations and permutations and cant seem to figure it out

    ta for all the help so far folks!
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hello,

    basically, none of the observed problems is related to Altera specific issues, it's simply a matter of syntax not corresponding to VHDL rules. The code would not compile with any other RTL compiler or simulator to my opinion.

    The error messages are referencing to specific code lines, normal procedure is to start with the first error message and try to understand the cause.

    --- Quote Start ---

    Error: VHDL syntax error at basic_func.vhd(26) near text "entity";

    --- Quote End ---

    You are defining an entity inside of a package body, this isn't a legal VHDL construct.

    Possible parts of a package body are according to VHDL sepecification

    --- Quote Start ---

    package_body_declarative_item ::=

    subprogram_declaration

    | subprogram_body

    | type_declaration

    | subtype_declaration

    | constant_declaration

    | shared_variable_declaration

    | file_declaration

    | alias_declaration

    | use_clause

    | group_template_declaration

    | group_declaration

    --- Quote End ---

    (I'm referring to IEEE 1076 instead of a compiler manual, cause they sometimes leave out some rarely used part of the specification. But what can be found in IEEE 1076 obviously isn't legal VHDL)

    Generally entities are declared in separate design units rather than packages. This can be in the same file as the package, but after end of package definition.

    Regards,

    Frank
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    hey thanks for persevering with this frank. :o

    thanks for that, I must try and get a better tutorial site as this is pretty much cut and paste from the one i'm using currently, so thought that was supposed to go in there, seemed a bit strange alright!

    will try this when I get back to it