Forum Discussion
Altera_Forum
Honored Contributor
18 years agoHello,
basically, none of the observed problems is related to Altera specific issues, it's simply a matter of syntax not corresponding to VHDL rules. The code would not compile with any other RTL compiler or simulator to my opinion. The error messages are referencing to specific code lines, normal procedure is to start with the first error message and try to understand the cause. --- Quote Start --- Error: VHDL syntax error at basic_func.vhd(26) near text "entity"; --- Quote End --- You are defining an entity inside of a package body, this isn't a legal VHDL construct. Possible parts of a package body are according to VHDL sepecification --- Quote Start --- package_body_declarative_item ::= subprogram_declaration | subprogram_body | type_declaration | subtype_declaration | constant_declaration | shared_variable_declaration | file_declaration | alias_declaration | use_clause | group_template_declaration | group_declaration --- Quote End --- (I'm referring to IEEE 1076 instead of a compiler manual, cause they sometimes leave out some rarely used part of the specification. But what can be found in IEEE 1076 obviously isn't legal VHDL) Generally entities are declared in separate design units rather than packages. This can be in the same file as the package, but after end of package definition. Regards, Frank