Honored Contributor
Honored Contributorhi
thanks for that has solved the most alarming errors alright but still have a slew of errors. may be something fundamental as we are working from someone else's notes and they are not for Quartus (Xilinx Foundation synthesis program.), just VHDL! errors now are as:Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition
Info: Processing started: Mon Mar 10 16:55:35 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off buzzer_structural -c buzzer_structural
Error: VHDL syntax error at basic_func.vhd(26) near text "entity"; expecting "end", or a declaration statement,
Error: VHDL syntax error at basic_func.vhd(29): name used in construct must match previously specified name "basic_func"
Error: Ignored construct basic_func at basic_func.vhd(24) because of previous errors
Error: VHDL error at basic_func.vhd(31): entity "AND2" is used but not declared
Error: VHDL error at basic_func.vhd(33): object "out1" is used but not declared
Error: VHDL error at basic_func.vhd(39): object "std_logic" is used but not declared
Error: Ignored construct OR2 at basic_func.vhd(37) because of previous errors
Error: VHDL error at basic_func.vhd(42): entity "AND2" is used but not declared
Error: VHDL error at basic_func.vhd(44): object "out1" is used but not declared
Error: VHDL syntax error at basic_func.vhd(46) near text "end"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"
Error: VHDL syntax error at basic_func.vhd(46) near text ";"; expecting "is"
Info: Found 0 design units, including 0 entities, in source file basic_func.vhd
Error: Quartus II Analysis & Synthesis was unsuccessful. 11 errors, 0 warnings
Error: Processing ended: Mon Mar 10 16:55:36 2008
Error: Elapsed time: 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 11 errors, 0 warnings
