Counters in cascade won't advanced on clock transistion

Using QUARTUS 2's functional simulation have always worked fully till QUARTUS 2 version 8 and 9. Here's my problem.

The details of the circuit are unimportant, for, it's obvious by reading what follows.

A circuit is made of 2 counters with a load input each and of course a clock input. The decoded output of the first one (clock generated at a certain count) triggers the clock input of the second counter while loading itself with 0 (the counter that has generated the decoded output also have it's load input connected to the decoded output).

The problem is that when I simulate the circuit with QUARTUS 2 version 7, the second counter counts up as it should each time the first counter resets itself to 0 by loading itself with binary 0 . But, when I simulate the same circuit with QUARTUS 2 versions 8 and up, the second counter waveforms don't show up anymore staying at count 0 all the time.

I know you're gonna say it's a normal delay type problem because while the first counter is loading itself with 0, it's decoded output never took place, thus never producing the clock that is supposed to trigger the second counter's clock input. In the real world, the physical circuit works fine, but does not simulate properly with QUARTUS 2 version 8 and up, but is with version 7. With a real logic analyzer, all waveforms show up correctly and I've simulated the circuit with another piece of software (GALAXY and Active HDL) and everything shows up correctly.

Is there a set up to be done when simulating with version 8 and up that wasn't needed in version 7?

Thanks for any comment and suggestions !!!

Regards ...