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Altera_Forum's avatar
Altera_Forum
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13 years ago

counter design using sopc builder

Hi, I had created a new component counter and also its slave interface by writing the hdl code and then included as a component using new component wizard in sopc builder.I then exported the output external to nios-ii using LED as PIO. System generation is also successful.But the only problem i am facing is how to initiate the counter using NIOS-II SBT ECLIPSE tool and how to initialise the on-chip memory.I included my c code.please verify the code and tell me the modifications.

Thank you in advance

c code:# include<io.h># include<system.h># include<stdio.h># define LED_DATA_BASE 0X00002000# define IORD_LED_DATA(LED_DATA_BASE,OFFSET)

alt_main()

{

int i;

for(i=0;i<=3;i++)

{

IORD_LED_DATA(LED_DATA_BASE,i);

}

}

//whether the code above is correct for a 4-bit counter controlled using nios-ii

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I don't understand what you did. Did you create a component with an avalon interface, or did you connect it to a PIO? 

    #define IORD_LED_DATA(LED_DATA_BASE,OFFSET)
    This is a reading macro, so you are just reading 4 different registers in the LED component, but not doing anything with the values read. What do you want to do exactly?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I had designed counter component as an avalon interface.But i used LEDS to display the results of counter

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    my component is:

    module counter(clk,clr,q);

    input clk,clr;

    output [7:0]q;

    reg [7:0]tmp;

    always @ (posedge clk or posedge clr)

    begin

    if(clr)

    tmp <= 8'b00000000;

    else

    tmp<=tmp+1'b1;

    end

    assign q=tmp;

    endmodule

    //slave interface

    module counter_slave_interface(clock,resetn,readdata,to_lights);

    input clock,resetn;

    output [7:0] readdata;

    output [7:0] to_lights;

    wire [7:0] to_reg,from_reg;

    counter my_instance(.clk(clock),.clr(resetn),.q(from_reg));

    assign to_lights=from_reg;

    assign readdata=from_reg;

    endmodule

    whether i designed it correct or not?i need the exact c code to initialize the counter.thank you
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I don't think it's very useful to connect your counter output directly to the leds. It will change so fast that you won't see anything. You could monitor its value with SignalTap though.

    I don't know a lot about Verilog but I find this strange:
    always @ (posedge clk or posedge clr)
    clr isn't a clock, you should wait for either a positive edge on clk, or a high value on clr. I'm not sure how Altera would synthesize this, but maybe someone that knows Verilog better can answer.

    As for your C code, you are currently reading 4 registers at 4 different addresses, but your component only has 1. You should only read at the base address, with offset 0. Except for that it looks ok, now you should do something with the value you read back.