counter design using sopc builder

I don't think it's very useful to connect your counter output directly to the leds. It will change so fast that you won't see anything. You could monitor its value with SignalTap though.

I don't know a lot about Verilog but I find this strange:

always @ (posedge clk or posedge clr)

clr isn't a clock, you should wait for either a positive edge on clk, or a high value on clr. I'm not sure how Altera would synthesize this, but maybe someone that knows Verilog better can answer.

As for your C code, you are currently reading 4 registers at 4 different addresses, but your component only has 1. You should only read at the base address, with offset 0. Except for that it looks ok, now you should do something with the value you read back.