counter design using sopc builder

my component is:

module counter(clk,clr,q);

input clk,clr;

output [7:0]q;

reg [7:0]tmp;

always @ (posedge clk or posedge clr)

begin

if(clr)

tmp <= 8'b00000000;

else

tmp<=tmp+1'b1;

end

assign q=tmp;

endmodule

//slave interface

module counter_slave_interface(clock,resetn,readdata,to_lights);

input clock,resetn;

output [7:0] readdata;

output [7:0] to_lights;

wire [7:0] to_reg,from_reg;

counter my_instance(.clk(clock),.clr(resetn),.q(from_reg));

assign to_lights=from_reg;

assign readdata=from_reg;

endmodule

whether i designed it correct or not?i need the exact c code to initialize the counter.thank you