Count enable vs Clock enable

Question

This may be a stupid question :confused: but I'm having a hard time with it. every time I think I get it I get confused again. can someone please explaing this? what happens with lets say a simple counter if it has a count enable, or a clock enable?

help! I'm trying to create a pulse with the FPGA starter kit, but i want an outside signal to control whether the pulse will be created or not.

altera_forum · Answer

Clock enable affects all synchronous activities (sload, sset, or sclr.) and stops counting.   Count Enable stops the counter from counting. You are still able to use sload, sset, or sclr.

altera_forum · Answer

Thank you!

altera_forum · Answer

https://www.dropbox.com/s/8z2rgxvisni71y6/syncdesign2.pdf?dl=0

Forum Discussion

Count enable vs Clock enable

3 Replies

Recent Discussions

Cyclone-V SCFIFO - adding ECC to M10K/MLAB/Auto memory

Will serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?

System PLL of Agliex5 PCIE example design cannot be locked after configuration

JTAG Chain Broken on Agilex 7-I Dev Kit

Request for Cyclone V Pinout File Information