Could some one explain some thing in this schematic please :)

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every thing makes sense apart from the following FPGA pins

pins 26,81 held high to 1.2v

pins 27,80 held to ground

why are these 'random' pins held high and to ground like this?

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When you are designing with FPGAs, there are a few documents you need to refer to. First is the handbook for the device:

http://www.altera.com/literature/lit-cyc2.jsp

On this page there is a link to the device pin outs:

http://www.altera.com/literature/lit-dp.jsp?category=cyc%20ii&showspreadsheet=y

If you look at the PDF for the device in the schematic:

http://www.altera.com/literature/dp/cyclone2/ep2c5.pdf

It tells you that pin 26+27 on the T144 page are either IO or an LVDS pair, and the same goes for 80+81.

If the design was planning on using LVDS, then Bank 1's VCCIO would need to be 2.5V. The schematic shows it as 3.3V.

There is no reason for these signals to be pulled to ground or any other voltage. The pull-up to 1.2V is wrong, since 1.2V is not a valid logic level for a 3.3V I/O.

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would the FPGA function as normal if they where just left unused?

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Yes.

Cheers,

Dave

ah LVDS pairs

I have never come across these before. just did a bit of research on them and they make sense :) (not needed in my design though :))

thanks for all your help :)

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There is no reason for these signals to be pulled to ground or any other voltage. The pull-up to 1.2V is wrong, since 1.2V is not a valid logic level for a 3.3V I/O.

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The pinout file clarifies the point. As the text EP2C8 near the jumper already suggests, these pins have to be connected to GND and VCCINT when migrating to EP2C8. In so far, it's strictly required to connect them this way. The unusual point is to use jumpers in this place. Usually the migration pins would be connected directly to the power planes without jumpers if the design is prepared for the migration device.

Regards,

Frank

Hey Frank,

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As the text EP2C8 near the jumper already suggests, these pins have to be connected to GND and VCCINT when migrating to EP2C8.

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I didn't even see that text in the schematic. Thanks for spotting it :)

If I was reviewing that schematic, my review comment would be that this comment be improved, eg., put a dashed box around both resistors and change the note to 'Power connections on EP2C8'.

Cheers,

Dave

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If I was reviewing that schematic, my review comment would be that this comment be improved, eg., put a dashed box around both resistors and change the note to 'Power connections on EP2C8'.

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Right. It's not good that you need to review the pinout file to be sure about the purpose of this connections.

Iv got a little bit lost, so i do need these pins now?

where in the documentation should i be looking to gather this information for my self for future projects using different FPGA's :)

thanks :)

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Iv got a little bit lost, so i do need these pins now?

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It depends on what devices you want to load on your board. If you want to load either the EP2C5 or EP2C8 device on your board, then you need to have these extra power-pin option resistors.

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where in the documentation should i be looking to gather this information for my self for future projects using different FPGA's :)

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In the pinout files I linked to.

You should also synthesize a design with Quartus and then compare the .pin file it generates with the pins in your schematic to confirm you have every pin correct.

Cheers,

Dave

ok cool im not actually using the EP2C5 in my project but the Cyclone EP1C3 but figured this EP1C3 schematic would be close enough to copy from (i know the core io voltages are different :))

Im guessing i dont need these extra power pins on the EP1C3 i just need to connect up the standard VCCIO(3.3)/VCCINT(1.5) power pins :)

Thanks for all your help :)

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ok cool im not actually using the EP2C5 in my project but the Cyclone EP1C3

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Download the pinout for the EP1C3 and follow its directions.

Make sure you wire up the JTAG connector on your board. This will be the primary debug interface.

Make sure you assign clocks to clock input pins and any output clocks to PLL output pins.

Create an HDL design of all the pins you plan on using before you finalize the design. Read all of the Quartus warnings, and change any pins you need to.

Cheers,

Dave