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Altera_Forum
Honored Contributor
Honored ContributorCould some one explain some thing in this schematic please :)
Im very new to FPGA's and am using this attached schematic to crib from.
every thing makes sense apart from the following FPGA pins pins 26,81 held high to 1.2v pins 27,80 held to ground why are these 'random' pins held high and to ground like this? would the FPGA function as normal if they where just left unused? Thanks :)28 Replies
Altera_Forum--- Quote Start --- Do you need the EEPROM? If you have to plug the module into a USB port, then there is no harm in just programming the device when you need it. I'm pretty sure the FPGA pins on the JTAG header go to the JTAG pins on the FPGA. It would have been better if they went to the MPSSE pins, since if you want to use SignalTap, you have to use a USB-Blaster. If the board did have an EPCS4, then you can use the FPGA to program it. Cheers, Dave --- Quote End --- sadly my project needs the FPGA to be configured the second the board gets power and i don't have control over when the user might run some software to configure it (the dot matrix display the FPGA is updating needs constant scanning or it can burn out!!) so i definitely need the EPCS4 that's good to know you can use JTAG to program the EPCS4, ill have to play around with this method in the future :)- Altera_Forum--- Quote Start --- Im not quite sure what you mean here? is this some sort of resistor down to gnd? what does this achieve? --- Quote End --- A source termination is a resistor in series (in-line) with the clock trace, eg., device pin, then resistor, then the trace continues. This resistor should be between 20 and 40 Ohms. It allows you to match the impedance of the transmission line from the clock to the destination. It works well for point-to-point clock traces. If you do not have these resistors, and you have long traces, then you may see ringing on the clock edges. This ringing can cause issues with your design. Cheers, Dave
- Altera_Forum--- Quote Start --- ahhh yes sorry when u said Morphic II it did not click, now i remember that is the FTDI FPGA module :) i did have a good read about this when i was first researching this project and it does do exactly what i want!!! but it was missing the FPGA config eeprom and i was not 100% sure how i would add this into its design/ if it was even possible to program a FPGA config eeprom using JTAG. --- Quote End --- Do you need the EEPROM? If you have to plug the module into a USB port, then there is no harm in just programming the device when you need it. --- Quote Start --- looking at FPGA schematics none of the JTAG pins seam to go any where near the EPCS4 but im guessing you just connect it to the FPGA as normal and when you use JTAG it programs the FPGA and then the FPGA also writes the data to the EPCS4? --- Quote End --- I'm pretty sure the FPGA pins on the JTAG header go to the JTAG pins on the FPGA. It would have been better if they went to the MPSSE pins, since if you want to use SignalTap, you have to use a USB-Blaster. If the board did have an EPCS4, then you can use the FPGA to program it. Cheers, Dave
- Altera_Forum--- Quote Start --- 4) Put source terminations on anything that is a clock, eg., the DCLK output from the FTDI chip, the SCLK to the SPI connector, and the clock oscillator. --- Quote End --- Im not quite sure what you mean here? is this some sort of resistor down to gnd? what does this achieve? Thanks :)
- Altera_Forum
ahhh yes sorry when u said Morphic II it did not click, now i remember that is the FTDI FPGA module :) i did have a good read about this when i was first researching this project and it does do exactly what i want!!! but it was missing the FPGA config eeprom and i was not 100% sure how i would add this into its design/ if it was even possible to program a FPGA config eeprom using JTAG.
looking at FPGA schematics none of the JTAG pins seam to go any where near the EPCS4 but im guessing you just connect it to the FPGA as normal and when you use JTAG it programs the FPGA and then the FPGA also writes the data to the EPCS4? - Altera_Forum--- Quote Start --- id actually like to see how its done. --- Quote End --- See mophic_program_c.txt posted to this thread: http://www.alteraforum.com/forum/showthread.php?t=31448&page=4 Cheers, Dave
- Altera_Forum--- Quote Start --- Ok. I just figured I'd ask. Its easy. I have a Morph-IC board that is programmed using Passive Serial mode using MPSSE mode. I'd give you the code if you wanted to see it, but ... Working hardware is always a good reference :) Cheers, Dave --- Quote End --- hehe thanks, id actually like to see how its done. would give me more options for future projects :) but ill stick with my AS way for this project as i have it all working / i under stand it!!! / i have the software :) and i have already designed the pcb hehe :)
- Altera_Forum--- Quote Start --- dont really want to go down the multiplier / tri state route as i want to keep this design cheap and as simple as it can be --- Quote End --- Ok. I just figured I'd ask. --- Quote Start --- i have heard of this MPSSE mode and i know the FTDI can do it. but i did a bit of research on it and could not find much info on software that does the actual programming side of it --- Quote End --- Its easy. I have a Morph-IC board that is programmed using Passive Serial mode using MPSSE mode. I'd give you the code if you wanted to see it, but ... --- Quote Start --- so decided to go with the other method instead which i KNOW works as i have tested it on a demo rig i have built using this FPGA and the FTDI chip --- Quote End --- Working hardware is always a good reference :) Cheers, Dave
- Altera_Forum--- Quote Start --- That is correct, but you should be powering the 93LC46B at 5V, not 3.3V. Look at your schematic, both VCC and the pullup are currently to 3.3V. Cheers, Dave --- Quote End --- sorry i completely see your point now :) thanks :) --- Quote Start --- Why not use MPSSE mode for JTAG programming directly? You could wire the FTDI to the JTAG chain and then program either the FPGA or the EPCS device. You could add a multiplexer, or tri-state the FTDI pins, and still be able to use the external JTAG connector. Cheers, Dave --- Quote End --- dont really want to go down the multiplier / tri state route as i want to keep this design cheap and as simple as it can be the JTAG header doesn't really need to be there at all. its just for the first prototype pcb really just for backup - when in production i wont even solder a header onto it! i have heard of this MPSSE mode and i know the FTDI can do it. but i did a bit of research on it and could not find much info on software that does the actual programming side of it. so decided to go with the other method instead which i KNOW works as i have tested it on a demo rig i have built using this FPGA and the FTDI chip :) it comes with a really nice c library i can wrap up in a nice little firmware upgrade tool i can give to people who want to update the firmware on this device in the future :)
- Altera_Forum--- Quote Start --- I want to configure this device using just JTAG for quick testing --- Quote End --- Why not use MPSSE mode for JTAG programming directly? You could wire the FTDI to the JTAG chain and then program either the FPGA or the EPCS device. You could add a multiplexer, or tri-state the FTDI pins, and still be able to use the external JTAG connector. Cheers, Dave
