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every thing makes sense apart from the following FPGA pins
pins 26,81 held high to 1.2v
pins 27,80 held to ground
why are these 'random' pins held high and to ground like this?
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When you are designing with FPGAs, there are a few documents you need to refer to. First is the handbook for the device:
http://www.altera.com/literature/lit-cyc2.jsp On this page there is a link to the device pin outs:
http://www.altera.com/literature/lit-dp.jsp?category=cyc%20ii&showspreadsheet=y If you look at the PDF for the device in the schematic:
http://www.altera.com/literature/dp/cyclone2/ep2c5.pdf It tells you that pin 26+27 on the T144 page are either IO or an LVDS pair, and the same goes for 80+81.
If the design was planning on using LVDS, then Bank 1's VCCIO would need to be 2.5V. The schematic shows it as 3.3V.
There is no reason for these signals to be pulled to ground or any other voltage. The pull-up to 1.2V is wrong, since 1.2V is not a valid logic level for a 3.3V I/O.
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would the FPGA function as normal if they where just left unused?
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Yes.
Cheers,
Dave
Honored Contributor
