Hello, The same process is giving issues once again: # ** Error: (vsim-3170) Could not find 'C:\Users\Alfonso\Desktop\PFC\simulation\modelsim\ rtl_work.TB_PFC_main'.# Error loading design# Error: Error loading design # Pausing macro execution # MACRO ./PFC_run_msim_rtl_vhdl.do PAUSED at line 34 I remember to delete the work folder to be able to compile a library that need that according to a modelsim tutorial: http://doc.union.edu/118/se_tutor.pdf (http://doc.union.edu/118/se_tutor.pdf) I have to do vcom <vhdl files .vhd> # do this for all the files cause it had to be done in the work folder, this may have caused the issue. i'm lost, can anyone help me?.

--- Quote Start --- Please, can anyone help me? --- Quote End --- The VHDL code is trying to use a component compiled into the rtl_work library. You can either compile your code into rtl_work via; vsim> vlib rtl_work vsim> vmap rtl_work [pwd]/rtl_work vsim> vcom -work rtl_work <your VHDL files> or you can simply map the rtl_work library to the same location as the work directory, eg., assuming you have created your work directory in the same folder you are working in via vsim> vlib work vsim> vmap work [pwd]/work then you can tell Modelsim to look in the work directory for the rtl_work components too by mapping it via vsim> vmap rtl_work [pwd]/work (You don't need the [pwd] statement if you don't want to use absolute paths in your .ini or .mpf file). Cheers, Dave

--- Quote Start --- The VHDL code is trying to use a component compiled into the rtl_work library. You can either compile your code into rtl_work via; vsim> vlib rtl_work vsim> vmap rtl_work [pwd]/rtl_work vsim> vcom -work rtl_work <your VHDL files> --- Quote End --- Hello, by typing this, how do you fill <your vhdl files>, by typing my vhdl files root (C:\Users\Alfonso\Desktop\PFC\altera) returns this: (I typed vsim> vcom -work rtl_work C:\Users\Alfonso\Desktop\PFC\altera) # Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 2011# ** Error: (vcom-7) Failed to open design unit file "C:UsersAlfonsoDesktopPFCltera" in read mode.# Invalid argument. (errno = EINVAL)# E:/altera/11.1sp2/modelsim_ase/win32aloem/vcom failed. --- Quote Start --- or you can simply map the rtl_work library to the same location as the work directory, eg., assuming you have created your work directory in the same folder you are working in via vsim> vlib work vsim> vmap work [pwd]/work then you can tell Modelsim to look in the work directory for the rtl_work components too by mapping it via vsim> vmap rtl_work [pwd]/work (You don't need the [pwd] statement if you don't want to use absolute paths in your .ini or .mpf file). Cheers, Dave --- Quote End --- It did not work, assuming [pwd] is written as [pwd] litterally (if it is a root instead, tell me) after typing those three lines literally as you did it continues returning me: # ** Error: (vsim-3170) Could not find 'C:\Users\Alfonso\Desktop\PFC\simulation\modelsim\rtl_work.TB_PFC_main'.# Error loading design# Error: Error loading design # Pausing macro execution # MACRO ./PFC_run_msim_rtl_vhdl.do PAUSED at line 34 Please help me i cannot test my code till this is solved.

--- Quote Start --- by typing this, how do you fill <your vhdl files>, by typing my vhdl files root (C:\Users\Alfonso\Desktop\PFC\altera) returns this: (I typed vsim> vcom -work rtl_work C:\Users\Alfonso\Desktop\PFC\altera) --- Quote End --- You've passed it a directory, not a VHDL file. You need to pass the vcom command the files that end in .vhd. You need to compile all of your files into the work library. If you are using Modelsim-ASE, then you do not need to compile Altera libraries. Cheers, Dave

Thank you for the effort. I typed: ... vcom -work rtl_work fixed_float_types_c.vhdl and it returned: # Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 2011# ** Error: (vcom-7) Failed to open design unit file "fixed_float_types_c.vhdl" in read mode.# No such file or directory. (errno = ENOENT)# E:/altera/11.1sp2/modelsim_ase/win32aloem/vcom failed. I moved from desktop to D: and tried again but failed with the same code, i try giving them write licence to all project files and folders, also with that failed. Alfonso.

Could not find rtl_work.TB.vhd | Altera Community

80 Replies

Altera_Forum
Honored Contributor
13 years ago
Try removing -L rtl_work from the command line argument.

Your script creates a folder named rtl_work, and then maps it to the VHDL library work. There is no library named rtl_work, so it should not be listed with the -L option.

Alternatively,

vsim -t ps TB_PFC_main

should also work. Modelsim is pretty good about locating VHDL libraries.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
Sorrry sorry i know the cause of the problem. the top level entity testbench name was incorrect.

sorry, don't kill me even i deserve, cause i'm the stupiest in the world.
Altera_Forum
Honored Contributor
13 years ago
http://i50.tinypic.com/1zvcutj.jpg

It wwwwwwwwooooooooooooooooooorrrrrkkkkkkkkkssssssssss!!!!!!!!!!!! Endorsing you dave!!!!!!!!!! One gwylllllion thanks !!!!!!!!!!!!!!
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
Sorrry sorry i know the cause of the problem. the top level entity testbench name was incorrect.

sorry, don't kill me even i deserve, cause i'm the stupiest in the world.

--- Quote End ---

The lesson you should learn is to read the messages. The tools are generally pretty good at telling you what they cannot understand.

--- Quote Start ---
It wwwwwwwwooooooooooooooooooorrrrrkkkkkkkkkssssssssss!!!!!!!!!!!! Endorsing you dave!!!!!!!!!! One gwylllllion thanks !!!!!!!!!!!!!!
--- Quote End ---

You're welcome.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
The lesson you should learn is to read the messages. The tools are generally pretty good at telling you what they cannot understand.

You're welcome.

Cheers,
Dave
--- Quote End ---

The most important is not having fear to command tools like modelsim, is such a fear, that disables you to think, even tough quartus is for two years old children compared to modelsim, it is terribly difficult.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
The most important is not having fear to command tools like modelsim, is such a fear, that disables you to think, even tough quartus is for two years old children compared to modelsim, it is terribly difficult.
--- Quote End ---

Using the tools becomes much simpler if you learn how to use the Tcl scripting language. The nice thing about scripts is you can write comments in them to remind yourself why you did things. Using the GUI is not as useful, as if you do not use the tools for a while, you forget how to use it. Look at the modelsim_example.zip file I referred you to earlier, and look at this tutorial:

http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

It has both Quartus and Modelsim Tcl scripts.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
Thank you Thank you thank you Dave, you are the only one has helped me to the end, the only fact that you are not left alone, helps going on, it's unbelievable the grateful i am, if i am fast i can this weekend teat all my testbench & project and monday/tuesday/friday show it to my master teacher to make all conclusions and finish the project.

Thank you for your involvement.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
Using the tools becomes much simpler if you learn how to use the Tcl scripting language. The nice thing about scripts is you can write comments in them to remind yourself why you did things. Using the GUI is not as useful, as if you do not use the tools for a while, you forget how to use it. Look at the modelsim_example.zip file I referred you to earlier, and look at this tutorial:

http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

It has both Quartus and Modelsim Tcl scripts.

Cheers,
Dave
--- Quote End ---

Downloaded, i'll take a look as i can and surelly if i get a job on VHDL, ayway, the next year i'll degree in electronics since in my university only two subjects change from telecommunications to electronics, which i did as optative subjects on of these ones was the one that teached me VHDL. So i'll keep visiting this forum surelly, and here i know there are kind persons to ask to in case of complicated doubts.

Thank you!!!! See you.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
if i am fast i can this weekend test all my testbench & project and monday/tuesday/friday show it to my master teacher to make all conclusions and finish the project.
--- Quote End ---
When you synthesize and simulate the code, pay attention to the warning messages from the tools. For example, in the files you sent me yesterday, there were warnings about uninitialized variables and signals missing from process statements. Read each warning, and edit your code to clear the error. Clearing as many trivial syntax errors as possible will help you see the real problems.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
If you referd to "change the library those two packages are compiled into, eg., right click on the files, and set the library to rtl_work" -> work

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Could not find rtl_work.TB.vhd

80 Replies

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