Could not find rtl_work.TB.vhd

Hello and thank you for your involvement, i don't know how to make a permanent configuration of tcl commands, according to se_tutor (http://www.alteraforum.com/forum/se_tutor) chapter 14, Tcl commands are what we were typing on the modelsim console, but i've not found nothing talking about scripts.

Please help me i must have debugged my code for next wednesday, and i can't use modelsim due to errors.

PS: one thing if I use notepad++ to modify a .DO file, launching modelsim overwites it, so i don't know how to make permanent changes.

(http://www.alteraforum.com/forum/se_tutor)

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Hello and thank you for your involvement, i don't know how to make a permanent configuration of tcl commands, according to se_tutor (http://www.alteraforum.com/forum/se_tutor) chapter 14, Tcl commands are what we were typing on the modelsim console, but i've not found nothing talking about scripts.

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Scripts are just files that you run (source) in the Modelsim console. Basically you're just saving yourself some typing.

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Please help me ...

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I'm trying, but you appear to be missing some fundamental experience with these tools ... so lets see if we can fix that.

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PS: one thing if I use notepad++ to modify a .DO file, launching modelsim overwites it, so i don't know how to make permanent changes.

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I've never seen Modelsim overwriting files. How are you starting Modelsim? If you are starting Modelsim from Quartus, then it is probably Quartus that is modifying files, not Modelsim.

Please review the modelsim_example.zip tutorial on using Modelsim posted in this thread:

http://www.alteraforum.com/forum/showthread.php?t=32386

That example shows what a Modelsim Tcl script is.

Please explain the steps you are performing with Quartus and Modelsim to have the problem with overwriting files.

Cheers,

Dave

Good afternoon/Morning:

What i try to do is:

1st:

vcom -work rtl_work fixed_float_types_c.vhdl

vcom -work rtl_work fixed_pkg_c.vhdl

2nd they work as yesterday did then i close the console, cause if the console is stoped i cannot launch MS succesfully, and when i press the button rtl compilation (> and a register with a timing signal under > and the reg) it launches and then after a while:

# ** error: (vsim-3170) could not find 'c:\users\alfonso\desktop\pfc\simulation\modelsim\rtl_work.tb_pfc_main'.# error loading design# error: error loading design # pausing macro execution # macro ./pfc_run_msim_rtl_vhdl.do paused at line 34

or

Same happens if i launch pfc_run_msim_rtl_vhdl.do with nottepad ++ and write, save and close, and then launch rtl compilation:

-------------------------------------------------------------------

transcript on

if {[file exists rtl_work]} {

vdel -lib rtl_work -all

}

vlib rtl_work

vmap work rtl_work

vcom -work rtl_work fixed_float_types_c.vhdl

vcom -work rtl_work fixed_pkg_c.vhdl

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/IHW_UART.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/altera/fixed_float_types_c.vhdl}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/PLL.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/altera/fixed_pkg_c.vhdl}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/Pack.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProducteS.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProducteE.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProducteO.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/SumaStep.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProdAnteriorNE.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProdAnteriorNO.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProdAnteriorSO.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProdAnteriorSE.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProducteSE.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProducteSO.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProducteNO.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProducteNE.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProducteN.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/CNN.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/PFC_main.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/SumaStep1.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/SumaStep2.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/SumaStep3.vhd}

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/TB_PFC_main.vhd}

vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cycloneii -L rtl_work -L work -voptargs="+acc" TB_PFC_main

add wave *

view structure

view signals

run -all

-------------------------------------------------------------------

It is deleted which leads me to:

# ** error: (vsim-3170) could not find 'c:\users\alfonso\desktop\pfc\simulation\modelsim\rtl_work.tb_pfc_main'.

Hello, this is the testbench file i want to use, i'm planning to use this, in case you need to know it.

Alfonso

Look at the Tcl script again. It already has the lines:

vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/altera/fixed_float_types_c.vhdl}
vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/PLL.vhd}
vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/altera/fixed_pkg_c.vhdl}

Note how the code is being compiled into the library work.

Since it sounds like you are using Quartus to run Modelsim, use Quartus to change the library those two packages are compiled into, eg., right click on the files, and set the library to rtl_work (I think that is how you do it).

Alternatively, just edit the VHDL files and change rtl_work to just plain work, and then it'll work fine.

Cheers,

Dave

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Since it sounds like you are using Quartus to run Modelsim, use Quartus to change the library those two packages are compiled into, eg., right click on the files, and set the library to rtl_work (I think that is how you do it).

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Leads to quartus compilation error:

Error (10481): VHDL Use Clause error at ProducteN.vhd(4): design library "ieee_proposed" does not contain primary unit "fixed_pkg"

Error (10800): VHDL error at ProducteN.vhd(4): selected name in use clause is not an expanded name

Error (10481): VHDL Use Clause error at Pack.vhd(10): design library "ieee_proposed" does not contain primary unit "fixed_pkg"

Error (10800): VHDL error at Pack.vhd(10): selected name in use clause is not an expanded name

Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 4 errors, 1 warning

Error: Peak virtual memory: 316 megabytes

Error: Processing ended: Thu Sep 13 18:56:45 2012

Error: Elapsed time: 00:00:02

Error: Total CPU time (on all processors): 00:00:02

Error (293001): Quartus II Full Compilation was unsuccessful. 6 errors, 1 warning

I'm trying the alternative method.

PS: Properties->library-> rtl_work, if i return to erase rtl_work from the Properties->library-> rtl_work, quartus compilates ok.

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Alternatively, just edit the VHDL files and change rtl_work to just plain work, and then it'll work fine.

Cheers,

Dave

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Sorry neither fixed_float_types_c fixed_pkg_c contains the rtl_work name, and if you refered to PFC_run_msim_rtl_vhdl.vhdl changes, it erases them.

Alfonso.

If you referd to "change the library those two packages are compiled into, eg., right click on the files, and set the library to rtl_work" -> work

work leads to same situation as nothing there.

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Leads to quartus compilation error:

Error (10481): VHDL Use Clause error at producten.vhd(4): design library "ieee_proposed" does not contain primary unit "fixed_pkg"

Error (10800): VHDL error at producten.vhd(4): selected name in use clause is not an expanded name

Error (10481): VHDL Use Clause error at pack.vhd(10): design library "ieee_proposed" does not contain primary unit "fixed_pkg"

Error (10800): VHDL error at pack.vhd(10): selected name in use clause is not an expanded name

Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 4 errors, 1 warning

Error: Peak virtual memory: 316 megabytes

Error: Processing ended: Thu Sep 13 18:56:45 2012

Error: Elapsed time: 00:00:02

Error: Total CPU time (on all processors): 00:00:02

Error (293001): Quartus II Full Compilation was unsuccessful. 6 errors, 1 warning

I'm trying the alternative method.

PS: Properties->library-> rtl_work, if i return to erase rtl_work from the Properties->library-> rtl_work, quartus compilates ok.

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THIS ERROR IS POINTING TO MY PROJECT FILES INCLUDES!! But once again about ieeeproposed...

The pack file is this:

-------------------------------------------------------

-- Design Name : User Pakage

-- File Name : Pack.vhd

-- Function : Defines function for LFSR

-- Coder : Alexander H Pham (VHDL)

-------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

library ieee_proposed;

use ieee_proposed.fixed_pkg.all;

USE ieee.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

package Pack is

type info is array (1 to 78) of sfixed (1 downto -16);-- 78= 8*8 + 14/16 bordes

type templates is array (1 to 9) of sfixed (1 downto -16);

end;

package body Pack is

end package body;

But also my main includes:

library ieee_proposed;

use ieee_proposed.fixed_pkg.all;

with no error.

VHDL allows you to package components into libraries.

If you know how to use the tools, then its relatively easy to get libraries working. Since you are letting the tool create scripts for you, its a little harder.

To make your life simpler, just edit the VHDL files with

library ieee_proposed;

use ieee_proposed.fixed_package.all;

and change these two lines into the single line

use work.fixed_package.all;

Then both Quartus and Modelsim will look for all VHDL in the default work library.

Cheers,

Dave