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Altera_Forum's avatar
Altera_Forum
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16 years ago

Correct use of reset input of a FF. VHDL

Hello,

In my design I will process an image.

In part of my hardware I need to RESET some FLIP FLOPS when FVAL(frame valid) arrives.

Is bad if I use the signal FVAL directly connected to the reset input of the Flip FLop?

Please look the attached file.

If I give reset directly with the FVAL, it will use less resources, but I do not know if it is bad.

Or the reset must be always connected to the global reset.

Sorry for the dummy question.

Thanks.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    It's safer to use a synchronous reset instead of an asynchronous one like you are proposing. if FVAL signal is glitch free, it could work, however, i guess FVAL is synchronous to master clock and is preferable adding a synchronous reset signal to your hardware.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Selecting between async or sync reset is not a trivial issue.

    You need async reset at power-up, or when you have no clock yet, or when you can't afford the pipeline cycle (sync reset would reset the flip-flop in the next cycle, async would reset on "this" one).

    In either case you should synchronize the reset signal to the flip-flop clock.