Correct use of reset input of a FF. VHDL

Selecting between async or sync reset is not a trivial issue.

You need async reset at power-up, or when you have no clock yet, or when you can't afford the pipeline cycle (sync reset would reset the flip-flop in the next cycle, async would reset on "this" one).

In either case you should synchronize the reset signal to the flip-flop clock.