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Honored Contributor
Honored ContributorCorrect use of reset input of a FF. VHDL
Hello, In my design I will process an image. In part of my hardware I need to RESET some FLIP FLOPS when FVAL(frame valid) arrives. Is bad if I use the signal FVAL directly connected ...
Altera_ForumHonored Contributor
Honored ContributorSelecting between async or sync reset is not a trivial issue.
You need async reset at power-up, or when you have no clock yet, or when you can't afford the pipeline cycle (sync reset would reset the flip-flop in the next cycle, async would reset on "this" one). In either case you should synchronize the reset signal to the flip-flop clock.
