Converting Behavioral to Gate Level

If you mean a description using e.g. AND, OR, FFs? *.vo/*.vho are using the gate level, that is actually present in FPGA, these are LEs consisting of a LUT and a FF. The LUT logic uses basic logic equations, and thus can be displayed as a gate circuit, if you want to.

In the gate level file, it's represented twice, by a binary lut_mask, specific to the involved FPGA family and a comment with a readable logic equation. But it's AHDL (ABEL) syntax rather than Verilog or VHDL.

It's not producing a pretty printed HDL gate level file.