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Altera_Forum's avatar
Altera_Forum
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13 years ago

conver froms td_logic_vector to integer

hai every one i'm new to vhdl code and i got problem how to use decimal value instead of binary

for example

right_m<="1010001010";

left_m <="1011101110";

i want to convert it to

right_m<=650

left_m <=750

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity adel is

Port ( clock,rest : in STD_LOGIC;

input : in STD_LOGIC_VECTOR (4 downto 0);

left_p : out std_logic;

right_p : out std_logic);

end adel;

architecture Behavioral of adel is

type state is (forward,right60,left60);

signal pr_state,nx_state : state;

signal counter : std_logic_vector(9 downto 0) ;

signal left_m : std_logic_vector(9 downto 0) ;

signal right_m : std_logic_vector(9 downto 0) ;

begin

process(clock,rest)

begin

if(rest='1' ) then

counter<="0000000000";

right_p <= '0';

left_p<= '0';

elsif (rising_edge (clock))then

if(counter=800) then

counter<="0000000000";

else

counter<=counter+'1';

if(counter<right_m) then

right_p<='1';

else

right_p<='0';

end if;

if(counter<left_m) then

left_p<='1';

else

left_p<='0';

end if;

end if;

end if;

end process

process(clock,rest)

begin

if(rest = '1')then pr_state <= forward;

elsif(clock'event and clock ='1')then

pr_state <= nx_state;

end if;

end process;

process(pr_state,sensor_input)

begin

case pr_state is

----------------------forward----------------------------

when forward =>

if(input = "11000")then

nx_state <= right60;

right_m<= "1010001010";

left_m <= "1011101110";

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Don't use library std_logic_arith. It's a bad practice of vhdl. use instead numeric_std:

    library ieee;

    use ieee.std_logic_1164.all;

    use ieee.numeric_std.all;

    signal left_m : unsigned(9 downto 0) ;

    signal right_m : unsigned(9 downto 0) ;

    right_m<=to_unsigned(650, 10);

    left_m <=to_unsigned(750, 10);

    You cast the numbers to unsigned. The first parameter is the number and the second the bits amount.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    you can also try:

    right_m<=conv_std_logic_vector(650,10);

    left_m <=conv_std_logic_vector(750,10);
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    you can also try:

    right_m<=conv_std_logic_vector(650,10);

    left_m <=conv_std_logic_vector(750,10);

    --- Quote End ---

    If you use the vhdl 2008 compiler option in Quartus, then you can use the constructs:

    right_m <= 10D"650";

    left_m <= 10D"750";

    In addition, you will want to use ieee.numeric_std.all as the previous post suggested. Best, James
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    you can also try:

    right_m<=conv_std_logic_vector(650,10);

    left_m <=conv_std_logic_vector(750,10);

    --- Quote End ---

    But this is considered bad practise, as it requires the library ieee.std_logic_unsigned. This library should really be avoided, as it can cause confusion and problems when trying to use a bit more arithmetic.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    In addition to what others have said - if you have a std_logic_vector that is storing an integer, why are you using a std_logic_Vector at all? why not just use an integer? (unless its the top level).

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Don't use library std_logic_arith. It's a bad practice of vhdl. use instead numeric_std:

    library ieee;

    use ieee.std_logic_1164.all;

    use ieee.numeric_std.all;

    signal left_m : unsigned(9 downto 0) ;

    signal right_m : unsigned(9 downto 0) ;

    right_m<=to_unsigned(650, 10);

    left_m <=to_unsigned(750, 10);

    You cast the numbers to unsigned. The first parameter is the number and the second the bits amount.

    --- Quote End ---

    It could be easily converted to std_logic vector:

    right_m<= std_logic_vector(to_unsigned(650, 10));

    left_m <= std_logic_vector(to_unsigned(750, 10));
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Don't use library std_logic_arith. It's a bad practice of vhdl. use instead numeric_std:

    library ieee;

    use ieee.std_logic_1164.all;

    use ieee.numeric_std.all;

    signal left_m : unsigned(9 downto 0) ;

    signal right_m : unsigned(9 downto 0) ;

    right_m<=to_unsigned(650, 10);

    left_m <=to_unsigned(750, 10);

    You cast the numbers to unsigned. The first parameter is the number and the second the bits amount.

    --- Quote End ---

    thanx alot for ur help

    do u hv any good reference for vhdl becz i want to improve my self in coding
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    thenx every one for helping me

    any one has a good and easy reference to understand vhdl coding

    thanx alot