conver froms td_logic_vector to integer

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Don't use library std_logic_arith. It's a bad practice of vhdl. use instead numeric_std:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

signal left_m : unsigned(9 downto 0) ;

signal right_m : unsigned(9 downto 0) ;

right_m<=to_unsigned(650, 10);

left_m <=to_unsigned(750, 10);

You cast the numbers to unsigned. The first parameter is the number and the second the bits amount.

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It could be easily converted to std_logic vector:

right_m<= std_logic_vector(to_unsigned(650, 10));

left_m <= std_logic_vector(to_unsigned(750, 10));