Constrainst for data launched by negative edge

@ Kaz,

As usual, thank you for your helpful nature and sharing your inputs. :)

@ vlrean,

Here are my suggestions:

(1) Cypress provides one example for using their chip with Altera device. ( I came to know from pdf which you shared in last link.) It would be good idea to see SDC file being used in that example.

(2)

--- Quote Start ---

No, launch edge of external device can be configured to positive or negative edge. I have configured external device to launch data on negative edge thinking that data will come to FPGA center alligned.

--- Quote End ---

Please use positive edge of clock. In this way, there will be gap of 10ns between launch clock and latch clock. After configuring your device to launch data on positive edge, you need to modify your input delay constraints (Just need to remove -clock_fall.).

So, now your SDC should look like :

# Base clock

create_clock -period "100MHz" -name CLK_IN [get_ports CLK_IN]

# Virtual clock

create_clock -name CLK_IN_VIRT -period "100MHz"

# parameters of external device

set tCO_max 7

set tCO_min 0

set in_max_value [expr $tCO_max]

set in_min_value [expr $tCO_min]

set_input_delay -clock [get_clocks CLK_IN_VIRT ] -max $in_max_value [get_ports {DATA*}]

set_input_delay -clock [get_clocks CLK_IN_VIRT ] -min $in_min_value [get_ports {DATA*}]

This should give us better (in your case, I should say best so far ) timing margin.

(3) If both of above do not help, then you should contact Cypress saying you are running your clock on 100 MHz. In this case, what value you should consider for Tco(max) and Tco (min).

(4) Regarding Multicycle explanation, download TimeQuest User Guide by Ryan Scoville from following location: http://www.alterawiki.com/wiki/timequest_user_guide. It contains good description about Multicycle path (Page 55 ) as well as other timing constraints. In your case, previously, we applied multicycle path to 'shift the window'. But now, as you are going to use positive edge, this is not required. Please remove multi-cycle path related constraints from your SDC file.

Thank you for reading this big post.:)

Kind Regards,

Bhaumik