Constrainst for data launched by negative edge

Hi,

Thanks for reply kaz.

So as I understand you are saying that multicycle is not needed in my case, since data is sampled at same clock period? What do you mean by saying:

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You can either enter offset directly relative to falling edge as you did or modify it relative to latch edge at fpga pin

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.

How it can be modified?

So what to do next? Clock relationship seems to be correct by looking at TimeQuest waveform, but timing requirements are not met. Am I using tCO values for max/min delays in a wrong way or am I missing something else?

Thanks