Constrainst for data launched by negative edge

For input data to fpga, timequest needs to know data offset relative to its sampling clock edge. Thus what matters is getting the offset information right. You can either enter offset directly relative to falling edge as you did or modify it relative to latch edge at fpga pin.

Regarding multicycle path you are free to do that if needed at io but not internally. Inside fpga you can only apply it if indeed you are sampling any data after 1 or so clocks. For io this does not matter since as long as data stream is sampled correctly then it doesn't matter if there is delay of sampling. but io mulicycle does not relax timing on both tSU and tH, rather it relaxes on one member of this pair. Both still need not be violated.

Internal multicycle that are result of slow data can relax timing on both.

So in short it may not be needed in your case as it is a straight forward input case.

Incidentally, in theory any internal design can also be applied multicycle style as io but then it requires substantial and weird change of code to account for delay...in such cases both min and max delay must be accomplished so that tSU and tH are not violated.