Constrainst for data launched by negative edge

Hi,

Thanks for you response.

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(1) Our clock period is 10ns and Tco (Max) is 7. This seems large value to me. It may be worth to re-check this value.

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Here is timing parameters from external device http://www.cypress.com/file/136056/download (http://www.cypress.com/file/136056/download), page 9, table 3. Can you look at this paper, maybe I have missunderstood something?

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(2) Minimum Tco you have considered is 0. Can we take some larger value? You may like to ask to manufacturer of external device. It would relax some timing requirements.

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What value do you suggest? I will try to write to support of external device to ask for those values.

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(3) It seems that external device launches data only on negative edge. Is this correct?

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No, launch edge of external device can be configured to positive or negative edge. I have configured external device to launch data on negative edge thinking that data will come to FPGA center alligned.

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(4) One thing which we can do is to use Multicycle path between virtual clock and sampling clock. So that, instead of trying to capture data on next postive clock cycle, let ask it to capture data on second next positive edge. You need to add following constraints in your SDC file:

set_multicycle_path -setup -from [get_clocks CLK_IN_VIRT ] -to [get_clocks CLK_IN] 2

No need to provide multi-cycle for hold. It will automatically take based on above command.

BUT, in this case, I afraid we will violate hold timings.

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I have added set_multicycle_path for setup and setup violation is gone but hold time violation had increased even more. But then I added same set_multicycle_path for hold:

set_multicycle_path -hold -from [get_clocks CLK_IN_VIRT ] -to [get_clocks CLK_IN] 2

Now TimeQuest shows me that timing requirements are met. Here is setup:

https://www.alteraforum.com/forum/attachment.php?attachmentid=12726

And for hold:

https://www.alteraforum.com/forum/attachment.php?attachmentid=12727

Now I am a bit confused, can you explain set_multicycle_path cammand a bit more to me? Do we actualy making FPGA to capture data with next rising edge of clock with this command or this is only for timing analysis? I was thinking that set_multicycle_path cammand is useful when data changes in different rate than clock?

Thanks.