Constrainst for data launched by negative edge

Hello,

Sorry for taking time to respond.

Here are my thoughts:

(1) Our clock period is 10ns and Tco (Max) is 7. This seems large value to me. It may be worth to re-check this value.

(2) Minimum Tco you have considered is 0. Can we take some larger value? You may like to ask to manufacturer of external device. It would relax some timing requirements.

(3) It seems that external device launches data only on negative edge. Is this correct?

(4) One thing which we can do is to use Multicycle path between virtual clock and sampling clock. So that, instead of trying to capture data on next postive clock cycle, let ask it to capture data on second next positive edge. You need to add following constraints in your SDC file:

set_multicycle_path -setup -from [get_clocks CLK_IN_VIRT ] -to [get_clocks CLK_IN] 2

No need to provide multi-cycle for hold. It will automatically take based on above command.

BUT, in this case, I afraid we will violate hold timings.

Thank you,

Bhaumik