Constrainst for data launched by negative edge

Hi,

thank you for your response, Bhaumik.

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Here is what I would do if I am there.

(1) I would take one pll with following parameters:

-> Mode : Source synchronous mode ( https://www.altera.com/support/support-resources/operation-and-testing/pll-and-clock-management/pll-glossary.html#source_synchronous_mode )

-> Input clock : Clock which is coming from external device

-> Output clock 0 : With same frequency as input clock

(2) Then I would use pll's output clock 0 to sample incoming signals.

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In my design there are no free PLL left, so I can not use it.

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I have assumed here that incoming clock is continuous. Is this correct?

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Yes, clock is continous.

I have corrected my timing constrainst by your previos post. Interface works correctly and clock relationchip seems to be correct but TimeQuest shows me that timing requirements ar not met. What could be done to achieve timing requrements? Here is updated waveform:http://www.alteraforum.com/forum/attachment.php?attachmentid=12722&stc=1

For input delay I am using tCO value from external device tCOmax=7ns, tCOmin is not specified so i have entered tCOmin=0. For input delay values i am using tco and tco min method from AN433 pdf.

input maximum delay value = maximum trace delay for data + tco of external device – minimum trace delay for clock

input minimum delay value = min trace delay for data + tco min of external device – max trace delay for clock

For now i have excluded trace delays from formulas.

So my .sdc file looks like:

# Base clock
create_clock -period "100MHz" -name CLK_IN # Virtual clock
create_clock -name CLK_IN_VIRT -period "100MHz"
# parameters of external device
set tCO_max     7
set tCO_min     0
set in_max_value 
set in_min_value 
set_input_delay -clock  -clock_fall -max $in_max_value 
set_input_delay -clock  -clock_fall -min $in_min_value