Constrainst for data launched by negative edge

Hello,

By using following, Timequest will consider that data is launched by falling edge.

# Base clock

create_clock -period "100MHz" -name CLK_IN [get_ports CLK_IN]

# Virtual clock

create_clock -name CLK_IN_VIRT -period "100MHz"

set_input_delay -clock [get_clocks CLK_IN_VIRT ] -clock_fall -max $in_max_value [get_ports {DATA*}]

set_input_delay -clock [get_clocks CLK_IN_VIRT ] -clock_fall -min $in_min_value [get_ports {DATA*}]

changes compared to your constraints: I have removed -waveform option in create_clock for CLK_IN and have added -clock_fall in set_input_delay.

i am not sure how should your design be properly constrained. Hence I would not be able to provide to the point answer. Sorry.

There is one Application note (AN433 -Constraining and Analyzing Source-Synchronous Interfaces ). Just search on google and you will find it. It may be helpful.

one question : Which clock have you been using to capture data? Are you using clock directly coming into FPGA?

Thank you,

Bhaumik