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Honored Contributor
Honored ContributorConstraining DDR inputs
I'm working on an FPGA design which interfaces to a DDR ADC chip. I need to apply constraints to the ADC data and clock input ports. First I have a question about virtual clocks: It seems to me that ...
Altera_ForumHonored Contributor
Honored ContributorThank Rysc instead. :)
Regarding virtual clocks, they're also useful because the "real" clock in the FPGA and the "virtual" clock at the ADC can have different uncertainties (jitter, etc). In particular, if you use the "derive_clock_uncertainty" command (which you should...), you should use virtual clocks to get the correct results. So, as a rule of thumb, do use virtual clocks.
