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Honored Contributor
Honored ContributorConstraining DDR inputs
I'm working on an FPGA design which interfaces to a DDR ADC chip. I need to apply constraints to the ADC data and clock input ports. First I have a question about virtual clocks: It seems to me that ...
Altera_ForumHonored Contributor
Honored ContributorThanks, this was way more helpful than Altera's course on DDR timing constraints.
