Connection of pll_ref_clk in an Arria10 with one JESD204b receiver

I am using an Arria10 and I implement one JESD204b receiver to communicate with one ADC which has the following paramters LMF=422.

According to the user guide I should connect to the pll_ref_clk, the output of of an ATX_PLL. However when doing this, the tools complains that this is not feasible and require connection of the reference clock (from the pin) straight. Thus two questions:

• Is this correct?
• If yes, then what the ATX_PLL is for (since I have only one receiver over four lanes and no bonding clock connection is offer at the IP ports)

Thanks

Nicolas