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noria's avatar
noria
Icon for New Contributor rankNew Contributor
6 years ago
Solved

Connection of pll_ref_clk in an Arria10 with one JESD204b receiver

I am using an Arria10 and I implement one JESD204b receiver to communicate with one ADC which has the following paramters LMF=422. According to the user guide I should connect to the pll_ref_clk, th...
  • noria's avatar
    noria
    6 years ago

    HI

    Well the page 66 of the JESD204B IP specify that the transceiver PLL need to be out of the transceiver for Arria10 device (the one I am using).

    Regards

Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi ,

May I know where you find in the document ATX_PLL output to pll_ref_clk. The reference clock has to be connected from the dedicated clk input pins