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IonHide's avatar
IonHide
Icon for New Contributor rankNew Contributor
1 year ago

Connection between two inout ports

Hello, I need to connect the 10 inout pins(A) to 10 inout pins (B) based on the logic of the cntrl signal (C) with respect to clock.

i-e when C = 0 , connect port A to port B &
when C= 1 , connect port B to port A.
what is the syntax I could follow to acheive the same , while simulating It not showing the results as needed.

Regards.

5 Replies

  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor

    Hello,


    Do you have the verilog code? we can try to take look at it.


    regards,

    Farabi


    • IonHide's avatar
      IonHide
      Icon for New Contributor rankNew Contributor

      always @(posedge clk) begin

      if (C) begin

      B_out = A;

      A_en = 0;

      B_en = 1;

      end else begin

      A_out = B;

      A_en = 1;

      B_en = 0;

      end

      end

      assign A = A_en ? A_out : 10'bz;

      assign B = B_en ? B_out : 10'bz;

      where A, B are inout ports , C input signal& others are local registers.

      Regards.

      • FvM's avatar
        FvM
        Icon for Super Contributor rankSuper Contributor

        Hi,
        doesn't look bad. Don't know which problem you experience. First output after direction signal change will be invalid due to registered x_en signal. E.g. C 1->0, A_ out latches old B output, then deactivate B and enables A. Unregistered x_en may achieve intended behaviour.

        If you don't get reasonable output at all, it's probably due to testbench design fault.

  • NazrulNaim_Intel's avatar
    NazrulNaim_Intel
    Icon for Regular Contributor rankRegular Contributor

    Hello,


    Sorry for the delay. Regarding your issue, have you tried this coding before?


    // Declare registers for A, B, and control signals

    reg [9:0] A_out, B_out;

    reg A_en, B_en;

    reg [9:0] A, B;


    always @(posedge clk) begin

    if (C) begin

    // When C is high, transfer A to B

    B_out <= A; // Use non-blocking assignment

    A_en <= 0;

    B_en <= 1;

    end else begin

    // When C is low, transfer B to A

    A_out <= B; // Use non-blocking assignment

    A_en <= 1;

    B_en <= 0;

    end

    end


    // Drive A and B based on enable signals

    always @* begin

    if (A_en) begin

    A = A_out;

    end else begin

    A = 10'bz; // High impedance when not enabled

    end


    if (B_en) begin

    B = B_out;

    end else begin

    B = 10'bz; // High impedance when not enabled

    end

    end


    Hope that helps and do let me know if I can assist you further.


    Best regards,

    Nazrul Naim


  • NazrulNaim_Intel's avatar
    NazrulNaim_Intel
    Icon for Regular Contributor rankRegular Contributor

    Hello,

    As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

    Best regards,

    Nazrul Naim