New Contributor
New Contributoralways @(posedge clk) begin
if (C) begin
B_out = A;
A_en = 0;
B_en = 1;
end else begin
A_out = B;
A_en = 1;
B_en = 0;
end
end
assign A = A_en ? A_out : 10'bz;
assign B = B_en ? B_out : 10'bz;
where A, B are inout ports , C input signal& others are local registers.
Regards.
Super ContributorHi,
doesn't look bad. Don't know which problem you experience. First output after direction signal change will be invalid due to registered x_en signal. E.g. C 1->0, A_ out latches old B output, then deactivate B and enables A. Unregistered x_en may achieve intended behaviour.
If you don't get reasonable output at all, it's probably due to testbench design fault.
