Honored Contributor
Honored ContributorThe problem probably is that the camera, as Avalon-ST-Source, is 8-bit wide. The SDRAM memory is 32-bit wide. SGDMA should pack each 4-bytes incoming from the streaming source, and write them at once as 32-bit word.
There is also the issue of two clock domains - 50[MHz] for the main clock and about ~1[MHz] clock (was mistaken at the previous post) for the pixel clock (PCLK). I've tried putting DCFIFO for handling the former and Data Format Adapter for the latter, in two configurations: a. avalon-st-source (8-bit) -> data format adapter (8-bit to 32-bit) -> avalon-st dcfifo (32-bit, in_clk - pclk, out_clk - 50[mhz]) <-> sgdma (32-bit) -> sdram (32-bit)
b. avalon-st-source (8-bit) -> avalon-st dcfifo (8-bit, in_clk - pclk, out_clk - 50[mhz]) -> data format adapter (8-bit to 32-bit) <-> sgdma (32-bit) -> sdram (32-bit) Both of them didn't work. What eludes me is what happens at the DCFIFO<->SGDMA. I have a few questions - 1. If the SGDMA is driven by the main clk, and its "in" stream is connected to the "out" port of the DCFIFO, does it means that when in Nios I begin dma transfer it will start clocking the fifo at 50[Mhz] and will not transmit data whenever the fifo is empty - which will happen most of the time because the PCLK is much slower ? 2. If The Data Format Adapter is driven by PCLK, and it packs every four 8-bit symbols to 1 word, does it means that is will output data only at quarter rate of PCLK ? Or is it outputting some garbage in between? In that case what should be my in_clk for the DCFIFO? (configuration a) What is the best configuration to achieve this [8-bit/clk_A] to [32-bit/clk_B] streaming task? Thanks!
