Connect TSE MAC to HPS

Question

Before we start - I am a QSYS beginner, and a newcommer to embedded IP.

I am trying to connect the Altera TSE MAC to the HPS. All existing examples use a NIOS, FPGA DMA controllers and a large internal RAM for packet buffering. As the HPS should have it's own DMA engine, should I be able to connect the TX and RX ports of the TSE MAC to the AXI ports of the HPS, as I thought they accepted streaming and MM?

Do I still need to do what the other examples do - use a Scatter gather DMA controller? Instead of an onboard ram, can I just connect the memory ports to the SDRAM connected to the HPS (obviously restricting memory space?)

altera_forum · Answer

I'm a beginner at this myself. From what I can gather the correct approach seems to be to read/write data to memory from the FPGA side and then use software in the HPS side to access Ethernet. I'm thinking of defining an interface in QSYS (not sure how to do this yet) to the HPS. The DMA controller in the HPS can use it to get the ADC data I'm using the FPGA side to collect. I'd then have a Linux driver and application software in the ARM to send that off via Ethernet.

It might also be possible to have the FPGA code write the data to HPS memory and send it off from there. I wonder if that would use more resources than having that logic implemented by the HPS DMA controller.

altera_forum · Answer

Have a look at this: http://www.altera.com/support/examples/nios2/exm-net-std-de.html?gsa_pos=1&wt.oss_r=1&wt.oss=niosii-ethernet-standard-5cgtfd9e

It uses the SGDMA to move data to/from the TSE MAC. In our case, we're connecting the SGDMA Avalon-MM directly to the HPS SDRAM interface, although we have yet to code the driver and have it working...

altera_forum · Answer

It looks like that example design is booting from external CFI flash. Note that the reset vector is defined to be in the external flash. You still need some way to get boot code into the HPS.

altera_forum · Answer

--- Quote Start ---

It looks like that example design is booting from external CFI flash. Note that the reset vector is defined to be in the external flash. You still need some way to get boot code into the HPS.

--- Quote End ---

What does the boot vector have to do with the SGDMA/Ethernet subsystem? I believe this thread is dealing with how to connect the TSE MAC to the HPS, so I'm only referencing the Ethernet sub-system portion of the http://www.altera.com/support/examples/nios2/exm-net-std-de.html?gsa_pos=1&wt.oss_r=1&wt.oss=niosii-ethernet-standard-5cgtfd9e reference.

altera_forum · Answer

Update: We have run into issues with the SGDMA on our Cyclone V linux/SoC platform:

We tried to compile the altera module for the tse/sgdma. However it is not compiling:

CC [M] drivers/net/ethernet/altera/altera_tse.o

drivers/net/ethernet/altera/altera_tse.c: In function ‘tse_sgdma_add_buffer’:

drivers/net/ethernet/altera/altera_tse.c:311:2: error: implicit declaration of function ‘flush_dcache_range’ [-Werror=implicit-function-declaration]

It looks like we dont have the flush_dcache_range inside cacheflush.h to our processor.

Apparently, more people are suffering the same problem:

http://lists.rocketboards.org/pipermail/rfi/2013-august/000392.html

And the proposed solution to flush the dcache didnt work there.

There are more people trying to use the same driver (tse + sgdma) and they claim that it is working in kernel 3.12:

http://lists.rocketboards.org/pipermail/rfi/2014-january/001016.html

But, it looks like that the driver is for the new mSGDMA, and not for the SGMDA.

We have checked out the kernel 3.12 and have noticed differences on this driver. We are now exploring whether to use the mSGDMA or the SGDMA; will post updates here.

NB: the mSGDMA reference is http://www.alterawiki.com/wiki/file:modular_sgdma_de.zip

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Connect TSE MAC to HPS

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