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Tufts's avatar
Tufts
Icon for New Contributor rankNew Contributor
2 years ago

Confused: Can FPGA measure less than 0.1ns delay between digital pulses?

Hello! I am a beginner of FPGA and want to learn can I build FIR-like structures in FPGA to process multi-channels of high speed pulse train and detect less than 0.1ns delay between each pulse? I f...
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WZ2's avatar
WZ2
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi there,

1. Clock Speed: The input clock speed of an FPGA determines how fast the logic cells inside the FPGA can operate. This clock speed is used for internal processing and can be much lower than the data rates you mentioned (e.g., 1 GHz).


2. Max IO Speed: This refers to the maximum rate at which data can be transferred between the FPGA and external devices, like memory, other chips, or ADC/DAC. It's usually lower than the internal clock speed due to the overhead involved in data transfer.


3. Max Sampling Speed: This pertains to the maximum rate at which an ADC can sample incoming analog signals, and similarly, the maximum rate at which a DAC can convert digital data to analog. The high sampling rate you mentioned (e.g., 64 Gsps) represents the raw data rate at the analog level.

Best regards,

WZ